1. Field of the Invention
The invention relates to complementary field effect transistor linear amplifiers.
2. Description of the Prior Art
Integrated circuit amplifiers utilizing bipolar integrated circuit technology are well know in the art. Such amplifiers commonly utilize feedback to improve gain and stability characteristics for various types of amplifier circuits. More recently, linear circuits have been implemented utilizing MOS and CMOS (complementary metal oxide semiconductor field effect transistor) technology. However, the MOS and CMOS technologies have been more often utilized to implement digital integrated circuits, where substantial cost-performance advantages have been realized where moderate speed performance was acceptable and very low power dissipation was required. However, bipolar transistor circuitry has an inherent speed performance advantage over MOS or CMOS circuitry due to the inherently greater gain characteristics of a bipolar transistor requiring an equivalent amount of silicon chip surface area. Linear circuit applications have often required the additional gain and power handling capability of bipolar transistor circuitry, so until recently MOS and CMOS circuits have found rather limited application in the area of linear circuits. Feedback has normally been utilized in linear amplifiers by utilizing some type of feedback circuit to couple a signal from an output stage to an input of the subject amplifier, the input normally being the same input to which an input signal is normally coupled. Adjustment of the DC (direct current) output level of amplifiers has often been accomplished by providing a DC bias to the input of the amplifier, to which an AC signal is capacitively coupled, or by adjusting resistors and emitter bipass circuits of the input stage or intermediate stages of the amplifier.
A basic problem in cascading three or more direct coupled self biased CMOS linear amplifier stages is that any deviation from ideal self-bias conditions is amplified with the result that the output stage is driven toward either the positive or negative supply voltage levels.
In the context, the ideal condition referred to consists of the common drain voltage in a self-biased CMOS inverter stage equalling exactly one half the supply voltage. However, this is normally difficult to accomplish unless individual matched discrete devices are utilized. In the CMOS technology, the P channel and N channel MOSFETs have different gains and different threshold voltages, typically. Further, matching of similar devices on the same silicon chip for MOS and CMOS technologies is not nearly as close as similar matching of V.sub.BE voltages in bipolar linear integrated circuit technology. (In general, CMOS linear amplifiers of the prior art which provide reasonably high gain, and are direct coupled so as to provide both AC and DC gain over a reasonable bandwidth have been difficult to manufacture).